1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to a method for testing and repairing these devices in the field.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. After the chips have been tested and certified for shipment, upon sale to the users, the users generally depend upon the reliability of the chips for their own systems to function properly. As the line width of memory cells within a memory array circuit chip continue to shrink (now at less than half a micron), this reliability becomes more difficult to achieve. One of the challenges for the manufacturers of memory devices, is to increase memory capacity without decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that each of the memory cells within the memory array is functioning properly. This testing method is routinely done because it is not uncommon for a significant percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
In the past, chip memories have been tested using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. This testing technique is not available to users once the chips have been shipped, making it difficult to detect faulty memory cells at the user site. Even if test equipment is available to users, field repairs are expensive, time-consuming, and impractical.
In addition, some repairs of memories have also been performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the technical complexity of the repairing process, and moreover, fail to address the possibility of failure after shipment from the manufacturing facility.
Because of the complexity of field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. As used herein, the term "BIST" refers to the actual test, while "BIST unit" and "BIST circuitry" refer to the circuitry that performs BIST. Similarly, "BISR" refers to the process of builtin self repair, while "BISR unit" and "BISR circuitry" refer to the circuitry that performs BISR. BIST operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In particular, in a data retention test, a BIST unit writes a data value to a memory cell, waits for a pause interval, and subsequently reads the memory cell. By comparing the data written and subsequently returned from the memory cell, the BIST unit is able to determine whether the memory cell is faulty. If failing cells are present, the BISR circuitry reassigns the row or column containing the failing cell to a spare row or column in the memory array. Generally, BIST and BISR are performed each time power is applied to the system, and thus, latent failures that occur between subsequent system power-ups may be detected in the field.
At present, BIST and BISR are employed with static memories. Due to the higher storage capacity of dynamic memories, it would be desirable to apply BIST and BISR methods to dynamic memories. However, for dynamic memories, the inherent sensitivity of refresh time to temperature severely complicates the data retention test. Since, the refresh time of a dynamic memory cell decreases strongly with increasing temperature, it may not be possible to choose a fixed BIST pause time which will suffice to detect faulty memory cells at all temperatures. In other words, a pause time which is chosen to optimally detect faulty memory cells at a nominal powering-up temperature may result in one of the following: (a) missing faulty cells at power-up temperatures lower than the nominal temperature, or (b) false alarms, i.e. declaring normal cells to be faulty, at temperature higher than the nominal temperature. The power-up temperature is defined to be the temperature of the memory chip at the time power it applied.
Furthermore, since BIST and BISR are conducted at the conditions that prevail at the time the memory device is powered on, they may not identify temperature sensitive failures. While BIST and BISR may perform a data retention test at power-up, the temperature of the system at that time may not be sufficient to induce cell failures. Subsequently, however, the temperature of the system may increase to a point that one or more memory cells will fail. Since BIST and BISR have already been performed at system power-on, BISR does not redirect accesses to these cells, which may result in a catastrophic system error.
Another problem arises in connection with the fact that it is generally desirable for dynamic memories to have a large refresh interval to minimize memory bus bandwidth required for the refresh function during normal operation. However, this implies that the BIST may take an inordinately long time to perform a data retention test on a dynamic memory device.